74AUP1G125GW,125, IC: digital; buffer,line driver; Ch: 1; CMOS; SMD; TSSOP5; -40?125°C

The 74AUP1G125GW is a single non-inverting Buffer/Line Driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE) is HIGH. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. • High noise immunity• Input-disable allows floating input conditions• IOFF circuitry provides partial power-down mode operation• Low static power consumption, ICC = 0.9µA maximum• Latch-up performance exceeds 100mA per JESD 78 class II• Inputs accept voltages up to 3.6V• Low noise overshoot and undershoot <10% of VCC